The present invention relates to communication devices generally and, more particularly, to a circuit, method and/or architecture for improving the performance of a serial communication link.
Referring to FIG. 1, a block diagram illustrating a communications circuit 10 is shown. The circuit 10 comprises a number of ports 14a-14n. Each of the ports 14a-14n comprises receive block 16, a transmit block 18 and a multiplexer 20.
The ports 14a-14n are connected to each other via serial links 21a-21n and 22a-22n. The ports 14a-14n each comprise serial inputs 24a-24n, 26a-26n and 28a-28n, and serial outputs 25a-25n, 27a-27n and 29a-29n, respectively. The serial connection from each port 14a-14n to another port 14a-14n is in both directions (i.e., both receive and transmit communication). The data arrives in the transmit block 18a-18n from a parallel interface 15a-15n, respectively, for each port 14a-14n. The data is then transmitted through a selectable multiplexer 20a-20n to the serial outputs 25a-25n, 27a-27n and/or 29a-29n. The serial outputs 25a-25n, 27a-27n and/or 29a-29n transmit the data to one of the serial communication links 22a-22n. 
For the receive side, the data is received from one of the serial communication links 21a-21n or 22a-22n at the serial input 24a-24n, 26a-26n and/or 28a-28n and passed through the selectable multiplexer 20a-20n to the receive (RX) block 16. The receive block 16 then passes the data to one of the parallel interfaces 15a-15n. 
The selectable multiplexers 20a-20n can be configured by management registers or by interface pins. When the connection from a particular port 14a-14n for either transmit or receive needs to be changed, the configuration interface or the configuration registers pass this new information to the particular selectable multiplexers 20a-20b. For the receive side, the receiver 16 has to wait for a period of time to acquire a lock.
The performance of the circuit 10 is significantly reduced since the amount of time to acquire a lock to a new port is of the order of the time it takes to send a block of data. Such a condition occurs in data communication switches.
The present invention concerns a circuit comprising a plurality of communication devices each configured to receive and transmit one or more data packets in response to one or more control signals and a control circuit configured to generate the one or more control signals in response to the one or more data packets.
The objects, features and advantages of the present invention include providing a communication device that may (i) eliminate a lock time between successive transfers, (ii) improve the overall performance of the device, and/or (iii) conserve power.